
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.LCSE.all;

entity PICtop is
  port (
    Reset    : in  std_logic;           -- Asynchronous, active low
    Clk      : in  std_logic;           -- System clock, 20 MHz, rising_edge
    RS232_RX : in  std_logic;           -- RS232 RX line
    RS232_TX : out std_logic;           -- RS232 TX line
    switches : out std_logic_vector(7 downto 0);  -- Switch status bargraph
    Temp_L   : out std_logic_vector(6 downto 0);  -- Less significant figure of T_STAT
    Temp_H   : out std_logic_vector(6 downto 0));  -- Most significant figure of T_STAT
end PICtop;

architecture behav of PICtop is

-------------------------------------------------------------------------
  -- Component for RS232top
---------------------------------------------------------------------------

	component RS232top is
		port(
			Reset     	: in  std_logic;   -- Low_level-active asynchronous reset
			Clk       	: in  std_logic;   -- System clock (20MHz), rising edge used
			
			Data_in	  	: in  std_logic_vector(7 downto 0);-- Data from dipswitches
			Valid_D   	: in  std_logic;   -- Start_TX, TX button-- from spartan system, low when data is valid
			Ack_in    	: out std_logic;   -- ACK for data received, low once data-- has been stored
			TX_RDY    	: out std_logic;   -- System ready to transmit
			TD        	: out std_logic;   -- from spartan system-- RS232 Transmission line
			RD        	: in  std_logic;   -- from spartan system-- RS232 Reception line
			Data_out  	: out std_logic_vector(7 downto 0);  --rx by spartan system--barleds, from tx rs232
			Data_read 	: in  std_logic;   -- 
			Full      	: out std_logic;   -- Full internal memory
			Empty     	: out std_logic);  -- Empty internal memory
		end component;

-------------------------------------------------------------------------
  -- Component for ram
---------------------------------------------------------------------------

	component RAM is
		port(
			
			Reset 	: in std_logic;
			Clk 		: in std_logic;								
			Databus 	: inout std_logic_vector( 7 downto 0); ---data bus
			Address 	: in std_logic_vector(7 downto 0);  --address bus
			CS 		: in std_logic;			--chip select
			write_en : in std_logic;   --write enable
			OE 		: in std_logic;			--read enable
			switches : out std_logic_vector(7 downto 0); ---switch state
			Temp_L 	: out std_logic_vector(6 downto 0);		---7 segment display lowest temperature value of thermostat
			Temp_H 	: out std_logic_vector(6 downto 0));		---7 segment display highest temperature value of thermostat
		
		end component;


-------------------------------------------------------------------------
  -- Component for dma
---------------------------------------------------------------------------

	component DMA is
		port(
			
			Reset     : in  std_logic;--asynchronous reset
			Clk       : in  std_logic;--20 MHZ
   
	----------------recieve data from rs232 to dma--------------------------------
			RCVD_Data : in  std_logic_vector(7 downto 0);--
			RX_Full   : in  std_logic;						--status signal RX internal memory full--from rs232 to dma
			RX_Empty  : in  std_logic;						--status signal RX internal memory ---------from rs232 to dma
			Data_Read : out  std_logic;					--request to read data from the rs232
   
	--------------------transmit data from dma to rs 232------------------------------
			TX_RDY    : in  std_logic;							--state of machine serial tx
			ACK_out   : in  std_logic;								--ack for data rx from rs 232..data from rs232 to pc
			Valid_D   : out  std_logic;							--valid data sent to rs232TX
			TX_Data   : out  std_logic_vector(7 downto 0);		--send data to serial line
   
   -------------RAM------------------------------------------------------
			CS        : out  std_logic;								--chip select
			Write_en  : out  std_logic;								---write data to ram 
			OE        : out  std_logic;								--read  from ram
			Address   : out  std_logic_vector(7 downto 0); 		--address bus
			Databus   : inout  std_logic_vector(7 downto 0);	 --system data bus
	
	-----main control-----------------------------------------
			DMA_ACK   : in  std_logic; 								--recognition and sharing of buses by the main processor
			Send_comm : in  std_logic;									 --start of data tx
			DMA_RQ    : out  std_logic;								 --request for bus to the processor
			READY     : out  std_logic); 								 ---=1 when processor is idle, 0-> processor is busy 
		end component;

----------------------------------------------------
------Component for ALU
----------------------------------------------------

 component ALU
	port(
			Reset 			: in std_logic;
			Clk 				: in std_logic;
			u_instruction 	: in alu_op;-- U-instruction from the cpu
			FlagC 			: out std_logic;--carry flag
			FlagZ 			: out std_logic;--Zero flag
			FlagN 			: out std_logic;--carry bit Nibble flag
			FlagE 			: out std_logic;--error flag
			Databus			: inout std_logic_vector(7 downto 0);
			Index_Reg		: out std_logic_vector(7 downto 0)--index register
			);
	end component;

------------------------------------------------------
----component for main_control
------------------------------------------------------
component MAIN_CONTROL
	port(
			  Reset 			: in  STD_LOGIC;
           Clk   			: in  STD_LOGIC;
           --------ROM---------------------------------------
			  ROM_Data 		: in  STD_LOGIC_VECTOR (11 downto 0); --data bus program memory
           ROM_Addr 		: out  STD_LOGIC_VECTOR (11 downto 0);--written by main control--address bus program memory
           -----RAM------------------------------------------
			  RAM_Addr 		: out  STD_LOGIC_vector(7 downto 0);--written by main control--adress bus of data memory
			  RAM_CS 		: out  STD_LOGIC;--by main control
           RAM_Write 	: out  STD_LOGIC;--written by main control
           RAM_OE 		: out  STD_LOGIC;--written by main control
           -------DMA------------------------------------
			  Databus 		: inout  STD_LOGIC_vector(7 downto 0);
           DMA_RQ 		: in  STD_LOGIC;--from the DMA controler
           DMA_ACK 		: out  STD_LOGIC;--written by main control
           SEND_comm 	: out  STD_LOGIC;--written by main control--transmission of data 
           DMA_READY 	: in  STD_LOGIC;--from the DMA controller
			 --------ALU---------------------------------
			  u_instruction 	: out alu_op;
			  Index			 	: in std_logic_vector(7 downto 0);
			 --Flags--------------------------------------
           FlagZ 				: in  STD_LOGIC;
           FlagC 				: in  STD_LOGIC;
           FlagN 				: in  STD_LOGIC;
           FlagE 				: in  STD_LOGIC
			  );
			  
		end component;

---------------------------------------------------
------Component for ROM
----------------------------------------------------
component ROM
	port(
			Instruction     : out std_logic_vector(11 downto 0);  -- Instruction bus
			Program_counter : in  std_logic_vector(11 downto 0)--data bus of ROM
		 );
end component;




--------Internal Signals---------------------------------------------

signal FlagZ		:STD_LOGIC;
signal FlagC 		:STD_LOGIC;
signal FlagN 		:STD_LOGIC;
signal FlagE 		:STD_LOGIC;
------------------------------------------------------------- 
signal alu_op_s			:alu_op; 
signal Index_reg			: std_logic_vector(7 downto 0);
signal Instruction     	: std_logic_vector(11 downto 0); -- Instruction bus
signal Program_counter 	: std_logic_vector(11 downto 0); --written by main control
----------------------------------------------------------------------

-----------------dma------------------------------------------
signal RCVD_Data			:std_logic_vector(7 downto 0);--connects Data_out(rs232) n RCVD_Data(dma)
signal RX_Full				:std_logic;
signal RX_Empty			: std_logic;
signal TX_RDY				:std_logic;--signal to connect rs232 n dma of same name
signal Ack_out				:std_logic;--siganl to connect Ack_in (rs232) n ACK_out(dma)

----------ram-----------------------------------------------------
signal Databus				:std_logic_vector(7 downto 0);
signal Address				:std_logic_vector(7 downto 0);
signal CS					:std_logic;
signal OE					:std_logic;
signal Write_en			:std_logic;

--------------rs232-----------------------------------
signal Valid_D				:std_logic;
signal Data_read			:std_logic;--connects Data_read(rs232) to Data_Read(dma)
signal TX_Data 			:std_logic_vector(7 downto 0);
signal DMA_ACK				:std_logic;
signal Send_comm			:std_logic;
signal DMA_READY			: std_logic;
signal DMA_RQ				: std_logic;
signal RAM_CS				: std_logic;
signal RAM_Write			: std_logic;
signal RAM_OE				: std_logic;

begin  -- behavior

RS232_PHY: RS232top
    port map (
        Reset     => Reset,
        Clk       => Clk,
        Data_in   => TX_Data,
        Valid_D   => Valid_D,
        Ack_in    => Ack_out,
        TX_RDY    => TX_RDY,
        TD        => RS232_TX,
        RD        => RS232_RX,
        Data_out  => RCVD_Data,
        Data_read => Data_read,
        Full      => RX_Full,
        Empty     => RX_Empty
				);

-------------------------------------------------------------------------

full_ram: RAM
	port map(
			Reset			=>	Reset, 
			Clk 			=>	Clk,								
			Databus		=>	Databus,  							---data bus
			Address 		=>	Address, 							 --address bus
			CS 			=>	RAM_CS,											--chip select
			Write_en		=>	RAM_Write,   							 --write enable
			OE 			=>	RAM_OE,										--read enable
			switches		=>	switches,							  ---switch state
			Temp_L 		=>	Temp_L, 								---7 segment display lowest temperature value of thermostat
			Temp_H 		=> Temp_H
			);	

dma_controller:DMA

	port map(
			Reset			=>	Reset,           
			Clk   		=>	Clk,
			RCVD_Data	=>	RCVD_Data, --signal --to connect Data_out(rs232)
			RX_Full   	=>	RX_Full,
			RX_Empty  	=>	RX_Empty,
			Data_Read 	=>	Data_read,
			TX_RDY    	=>	TX_RDY,
			ACK_out   	=>	Ack_out,--ports are connected to the signals and then to each other through the signals
			Valid_D   	=>	Valid_D,
			TX_Data   	=>	TX_Data,
			CS        	=>	CS,
			Write_en   	=>	Write_en,--signal connected to ram n dma
			OE        	=>	OE ,
			Address   	=>	Address,
			Databus   	=>	Databus,
			DMA_ACK   	=>	DMA_ACK,
			Send_comm 	=>	Send_comm,
			DMA_RQ    	=>	DMA_RQ,
			READY      	=>	DMA_READY
			);

-------------------------------------------------------------------------------------

arith: ALU
	port map(
			Reset					=> Reset,           
			Clk 					=> Clk,
			u_instruction		=> alu_op_s, -- U-instruction from the cpu
			FlagC					=> FlagC,
			FlagZ					=> FlagZ,
			FlagN					=> FlagN,					--carry bit Nibble flag
			FlagE					=> FlagE,
			Databus				=> Databus,
			Index_Reg			=> Index_Reg 
			);
			
------------------------------------------------------------------------------------
Main_cont:MAIN_CONTROL
	
	port map(	
			  Reset				=> Reset,
           Clk					=>Clk,
           --------ROM---------------------------------------
			  ROM_Data 			=>Instruction, 		--data bus program memory
           ROM_Addr			=>Program_counter,	--written by main control--address bus program memory
           -----RAM------------------------------------------
			  RAM_Addr			=>Address,				--written by main control--adress bus of data memory
			  RAM_CS				=>RAM_CS,
           RAM_Write			=>RAM_Write,			--written by main control
           RAM_OE				=>RAM_OE,						--written by main control
           -------DMA-----------------------------------
			  Databus			=>databus,
           DMA_RQ				=>DMA_RQ,					--from the DMA controler
           DMA_ACK			=>DMA_ACK,				--written by main control
           SEND_comm			=>SEND_comm,			--written by main control--transmission of data 
           DMA_READY			=>DMA_READY	,				--from the DMA controller
           -------ALU----------------------------------
			  u_instruction	=>alu_op_s, 
			  Index				=>Index_reg,
           FlagZ				=>FlagZ,
           FlagC				=>FlagC,
           FlagN				=>FlagN,
           FlagE				=>FlagE 
			  );
--------------------------------------------------------------------------------------------------------
	AUTOMATIC:ROM
	port map(
				Program_counter	=> Program_counter,  --address bus of ROM
				Instruction  		=> Instruction
				);
	
end behav;

